Patterned backside stress engineering for transistor performance optimization

ABSTRACT

Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance.

The present patent application is a Divisional of Application No.10/949,463, filed Sep. 24, 2004.

TECHNICAL FIELD

This invention relates to semiconductor technology. In particular, thepresent invention relates to methods and apparatus for transistoroptimization by stress engineering.

BACKGROUND

In semiconductor processing, transistors may be formed on semiconductorwafers. The transistors may include a gate electrode, a source, a drain,and a channel region and may be NMOS (N Channel Metal OxideSemiconductor) or PMOS (P Channel Metal Oxide Semiconductor)transistors. The transistors and other devices may be interconnected toform integrated circuits (ICs). The ICs may then be packaged and sold tothe public. The performance of the ICs may depend on the performance ofthe transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is illustrated by way of example and not by way oflimitation in the figures of the accompanying drawings, in which thelike references indicate similar elements and in which:

FIG. 1 illustrates a cross sectional type view of an apparatus inaccordance with one embodiment of the present invention.

FIGS. 2A-2I illustrate cross sectional type views of a method inaccordance with one embodiment of the present invention.

FIG. 3 illustrates a cross sectional type view of an apparatus inaccordance with one embodiment of the present invention.

DETAILED DESCRIPTION

In various embodiments, an apparatus and method relating to inducingback side stresses on transistor regions are described. In the followingdescription, various embodiments will be described. However, variousembodiments may be practiced without one or more of the specificdetails, or with other methods, materials, or components. In otherinstances, well-known structures, materials, or operations are not shownor described in detail to avoid obscuring aspects of various embodimentsof the invention. Similarly, for purposes of explanation, specificnumbers, materials, and configurations are set forth in order to providea thorough understanding of the invention. Nevertheless, the inventionmay be practiced without specific details. Furthermore, it is understoodthat the various embodiments shown in the figures are illustrativerepresentations and are not necessarily drawn to scale.

Various operations will be described as multiple discrete operations inturn. However, the order of description should not be construed as toimply that these operations are necessarily order dependent. Inparticular, these operations need not be performed in the order ofpresentation.

Stress engineering transistor channels may provide enhanced transistorperformance. For example, NMOS (N Channel Metal Oxide Semiconductor)transistor performance may improve when the channel region of the NMOStransistor is under tensile stress while PMOS (P Channel Metal OxideSemiconductor) transistor performance may improve when the channelregion of the PMOS transistor is under compressive stress. Stressengineering may be broadly defined as providing tensile or compressivestress to a material. Briefly, embodiments of the present invention mayinclude independently inducing stress on transistors from the back sideof a substrate. More specifically, different back side stresses may beselectively applied to NMOS and PMOS transistor channels.

FIG. 1 illustrates a cross-sectional type view of an apparatus 100.Apparatus 100 includes a substrate 170 having a front surface 110 and aback surface 160. Front surface 110 may include NMOS transistor regions120 and PMOS transistor regions 130. Substrate 170 may also include NMOSback side stress engineering areas 140 and PMOS back side stressengineering areas 150. FIG. 1 illustrates back side stress engineeringareas 140, 150 on a substrate surface opposite the NMOS and PMOStransistor regions 120, 130, as further discussed below.

An example of the present invention having NMOS back side stressengineering areas 140 formed on the back surface 160 opposite NMOStransistor regions 120 and PMOS back side stress engineering areas 150formed under the back surface 160 opposite PMOS transistor regions 130is illustrated. In other embodiments, back side stress engineering areas140, 150 may both be formed under the back surface 160 or both may beformed on the back surface 160. In other embodiments, only one back sidestress engineering area may be formed opposite one transistor typeregion. Further, the disclosed invention is not limited to NMOS and PMOStransistor type regions or only two transistor type regions. In otherembodiments, more than two stress engineering areas may be selectivelyformed opposite more than two transistor type regions. In yet otherembodiments, the NMOS transistors, the PMOS transistors, or both mayinclude transistors having stress engineering performed during frontside transistor fabrication. Many other embodiments, such as differentback side stress engineering areas patterned over the same transistortype regions, may also be available by the methods of the presentinvention.

FIGS. 2A-2I illustrate a method, according to one embodiment of theinvention. Referring first to FIG. 2A, NMOS transistor regions 120 andPMOS transistor regions 130 may be formed on front surface 110 of astarting substrate 200 by known methods. Starting substrate 200 may be awafer or a die and may include monocrystalline silicon, silicon oninsulator, or other suitable materials. Starting substrate 200 may alsoinclude other layers or structures (not shown) that comprise insulative,conductive, or semiconductive materials, such as vias, dielectrics,metal traces, bumps, and others. FIG. 2A illustrates transistor regions120, 130 separated by a gap for clarity. In other embodiments,transistor regions 120, 130 may be immediately adjacent to each other orthey may be separated by trenches, for example.

The method may continue by mounting front surface 110 to a wafer supportsystem 210 by known methods as illustrated in FIG. 2B. Startingsubstrate 200 may be thinned by known methods to form a substrate 170having a back surface 160 as illustrated in FIG. 2C. In one embodiment,a diffusion barrier (not shown) including Titanium, Nickel, or othersuitable materials may be formed on back surface 160. The diffusionbarrier may provide a seed layer for subsequent Copper plating. In otherembodiments, the substrate may not be thinned or may not have adiffusion barrier formed thereon.

In FIG. 2D, a pattern 220 may be formed over back surface 160 ofsubstrate 170. In one embodiment, pattern 220 may selectively coverbackside areas opposite NMOS transistor regions 120 while exposing PMOStransistor regions 130. Pattern 220 may be formed by a photo-patterningprocess using a photoresist or a laminate or by a reductive thin filmdeposition, lithography, and etch process. In one embodiment, wafersupport system 210 may be made of glass or other suitable material andpattern 220 may be aligned to transistor regions 120, 130 by usingoptical pattern recognition through wafer support system 210.

The method may continue in FIG. 2E by forming PMOS back side stressengineering areas 150 opposite PMOS transistor regions 130. PMOS backside stress engineering areas 150 may be formed under back surface 160(as illustrated) or on back surface 160. In one embodiment, PMOS backside stress engineering areas 150 may be formed by atomic implant. Inone embodiment, the atomic implant may include Germanium to provide acompressive stress on the transistor channels of the transistors in PMOStransistor regions 130. In other embodiments, PMOS back side stressengineering areas 150 may include a thin film layer. As shown in FIG.2F, pattern 220 may be removed by known methods.

In FIG. 2G, a second pattern 230 may be formed over back surface 160 ofsubstrate 170. Second pattern 230 may selectively cover backside areasopposite PMOS transistor regions 130 while exposing backside areasopposite NMOS transistor regions 120. Second pattern 230 may be formedby a photo-patterning process using a photoresist or a laminate or by areductive thin film deposition, lithography, and etch process. In oneembodiment, wafer support system 210 may be made of glass or othersuitable material and second pattern 230 may be aligned to transistorregions 120, 130 by using optical pattern recognition through wafersupport system 210. In one embodiment, second pattern 230 may be theinverse of pattern 220. In such an embodiment, the same lithography maskmay be used if additive methods are used for one pattern and reductivemethods for the other.

In FIG. 2H, NMOS back side stress engineering areas 140 may be formedopposite NMOS transistor regions 120. NMOS back side stress engineeringareas 140 may be formed on back surface 160 (as illustrated) or underback surface 160. In one embodiment, NMOS back side stress engineeringareas 140 may include atomic implant or deposition or growth of a thinfilm. In one embodiment, NMOS back side stress engineering areas 140 maybe a nitride thin film that provides a tensile stress in the channelregions of the transistors in NMOS transistor regions 120. Pattern 220may be removed by known methods, as shown in FIG. 2I, and substrate 170may be released from wafer support system 210.

In other embodiments of the present invention, the method mayaccommodate additional transistor regions. Further, other methods forinducing back side stress, for example a Copper layer may be plated atdifferent temperatures in different regions, may be used.

FIG. 3 illustrates a cross-sectional type view of an apparatus 300.Apparatus 300 includes substrate 170 having front surface 110, backsurface 160, and an integrated heat spreader 310 attached to backsurface 160 by a thermal interface material 320. Front surface 110 mayinclude NMOS transistor regions 120 and PMOS transistor regions 130.Integrated heat spreader 310 includes thin portions 320 adjacent to NMOStransistor regions 120 and thick portions 330 adjacent to PMOStransistor regions 130. Integrated heat spreader 310 may selectivelyprovide back side stress engineering to substrate 170. Specifically,thick portions 330 may provide a greater compressive stress to PMOStransistor regions 130 than thin portions 320 provide to NMOS transistorregions 120. The thickness of thin portions 320 may be in a variety ofranges, including about 0.1 to 1.25 mm, about 0.25 to 1.1 mm, and about0.5 to 1.0 mm. The thickness of thick portions 330 may be in a varietyof ranges, including about 1.25 to 2.75 mm and about 1.5 to 2.5 mm.

In one embodiment, integrated heat spreader 310 may be attached at ahigh temperature to substrate 170 and integrated heat spreader 310 maybe cooled. Cooling integrated heat spreader 310 may cause a compressivestress on substrate 170 and thick portions 330 may provide a greatercompressive stress than thin portions 320. In one embodiment, integratedheat spreader 310 includes copper. Thermal interface material 320 may bea stiff material, such as gold-tin, in order to transmit the stress tosubstrate 170.

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure, material, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the invention. Thus, the appearances ofthe phrases “in one embodiment” or “in an embodiment” in various placesthroughout this specification are not necessarily referring to the sameembodiment of the invention. Furthermore, the particular features,structures, materials, or characteristics may be combined in anysuitable manner in one or more embodiments.

It is to be understood that the above description is intended to beillustrative, and not restrictive. Many other embodiments will beapparent to those of ordinary skill in the art upon reviewing the abovedescription. The scope of the invention should, therefore, be determinedwith reference to the appended claims, along with the full scope ofequivalents to which such claims are entitled.

1. An apparatus comprising: a substrate surface having a firsttransistor type region and a second transistor type region; and abackside stress region on a substrate surface opposite the firsttransistor type region.
 2. The apparatus of claim 1, wherein the backside stress region comprises at least one of an atomic implant or a thinfilm.
 3. The apparatus of claim 1, wherein the first transistor typeregion comprises a PMOS transistor, the second transistor type regioncomprises a NMOS transistor, and the back side stress region comprises aGermanium implant.
 4. The apparatus of claim 1, wherein the firsttransistor type region comprises a NMOS transistor, the secondtransistor type region comprises a PMOS transistor, and the back sidestress region comprises a nitride thin film.
 5. The apparatus of claim1, further comprising: a second backside stress region on a substratesurface opposite the second transistor type region.
 6. The apparatus ofclaim 5, wherein the first transistor type region comprises a NMOStransistor, the second transistor type region comprises a PMOStransistor, the back side stress region comprises a nitride thin film,and the second backside stress engineering region comprises a Germaniumimplant.
 7. The apparatus of claim 5, further comprising: a thirdtransistor type region on the substrate surface; and a third backsidestress region on a substrate surface opposite the third transistor typeregion.
 8. An apparatus comprising: a front surface of a thinned wafermounted to a wafer support system; a pattern on a back surface of thethinned wafer; and a backside stress region on the back surface of thethinned wafer.
 9. The apparatus of claim 8, wherein the wafer supportsystem comprises glass.
 10. The apparatus of claim 8, wherein the backside stress region comprises at least one of an atomic implant or a thinfilm.
 11. An apparatus comprising: a first surface of a substrate havinga PMOS transistor region and a NMOS transistor region; a first backsidestress region comprising an atomic implant on a substrate surfaceopposite the PMOS transistor region; and a second backside stress regioncomprising a thin film layer on the substrate surface opposite the NMOStransistor region.
 12. The apparatus of claim 11, wherein the atomicimplant includes a Germanium implant.
 13. The apparatus of claim 11,wherein the thin film layer includes a nitride layer.
 14. An apparatuscomprising: a first surface of a substrate having a first transistortype region and a second transistor type region; and a heat spreaderattached to a substrate surface opposite the first surface, the heatspreader having a portion opposite the first transistor type region thatis thinner than a portion opposite the second transistor type region.15. The apparatus of claim 14, wherein the first transistor type regioncomprises a NMOS transistor and the second transistor type regioncomprises a PMOS transistor.
 16. The apparatus of claim 14, wherein theportion opposite the first transistor type region is about 0.1 to 1.25mm thick and the portion opposite the second transistor type region isabout 1.25 to 2.75 mm thick.
 17. The apparatus of claim 14, wherein theportion opposite the first transistor type region is about 0.25 to 1.1mm thick and the portion opposite the second transistor type region isabout 1.25 to 2.75 mm thick.
 18. The apparatus of claim 14, wherein theportion opposite the first transistor type region is about 0.5 to 1.0 mmthick and the portion opposite the second transistor type region isabout 1.5 to 2.5 mm thick.
 19. The apparatus of claim 14, furthercomprising: a thermal interface material between the substrate surfaceopposite the first surface and the heat spreader.
 20. The apparatus ofclaim 19, wherein the heat spreader includes copper and the thermalinterface material includes gold-tin.
 21. A method comprising: forming apattern over a first surface of a substrate, the substrate having afirst transistor type region and a second transistor type region on asecond surface, the pattern covering at least a portion of the firstsurface opposite the second transistor type region and exposing at leasta portion of the first surface opposite the first transistor typeregion; and inducing a back side stress in the at least one firsttransistor type region.
 22. The method of claim 21, wherein inducing theback side stress includes implanting atoms into the first surface. 23.The method of claim 21, wherein inducing the back side stress includesproviding a thin film.
 24. The method of claim 21, wherein the firsttransistor type region comprises a PMOS transistor and the secondtransistor type region comprises a NMOS transistor.
 25. The method ofclaim 24, wherein inducing the back side stress includes implantingGermanium.
 26. The method of claim 21, wherein the first transistor typeregion comprises a NMOS transistor and the second transistor type regioncomprises a PMOS transistor.
 27. The method of claim 26, whereininducing the back side stress includes providing a nitride layer. 28.The method of claim 21, further comprising: forming a second patternover the first surface, wherein the second pattern covers at least aportion of the first surface opposite the first transistor type regionand exposes at least a portion of the first surface opposite the secondtransistor type region; and inducing a second back side stress in the atleast one second transistor type region using the second.
 29. The methodof claim 28, wherein inducing the back side stress includes copperplating at a first temperature and inducing the second backside stressincludes copper plating at a second temperature.
 30. The method of claim21, further comprising: mounting the second surface of the substrate toa wafer support system; thinning the substrate; and depositing adiffusion barrier on the first surface of the substrate.
 31. The methodof claim 21, further comprising: providing front side stress engineeringto the second transistor type region.
 32. The method of claim 21,wherein forming the pattern includes a photo-patterning process.
 33. Amethod comprising: selectively inducing stress to the back side of afirst transistor type region of a substrate having the first transistortype region and a second transistor type region.
 34. The method of claim33, wherein selectively inducing stress comprises at least one ofimplanting atoms or providing a thin film.
 35. The method of claim 33,further comprising: selectively inducing a second stress to the backsideof the at least one second transistor type region.
 36. The method ofclaim 33, wherein the first transistor type region comprises a PMOStransistor and inducing stress includes implanting Germanium atoms. 37.The method of claim 33, wherein the first transistor type regioncomprises a NMOS transistor and inducing stress includes providing anitride layer.